Strained semiconductor-on-insulator structures for semiconductor devices combine the benefits of two advanced techniques for performance enhancement, namely, semiconductor-on-insulator (SOI) technology and strained semiconductor technology. On the one hand, a strained SOI configuration offers various advantages associated with the insulating substrate, such as reduced parasitic capacitances and improved isolation. On the other hand, strained semiconductors provide improved carrier mobilities. Devices such as strained semiconductor metal-oxide-semiconductor field-effect transistors (MOSFETs) combine enhanced carrier mobilities with the advantages of insulating substrates.
One method of fabricating strained Si directly on an insulating layer involves using a thick graded SiGe buffer layer, chemical mechanical polishing (CMP), strained Si growth, wafer bonding to a handle wafer including an insulator, layer transfer, and SiGe etch back. Such a prior art method is disclosed, for example, in U.S. Application Publication No. 2003/003679 A1 to Doyle et al. This prior method has an intrinsic complication because wafer bonding requires very smooth surfaces, and graded SiGe films typically have a very rough surface which makes graded SiGe films not suitable for use in most wafer bonding processes. CMP is used in the prior art method to make the surfaces smoother, but CMP reduces the substrate manufacturability, especially for 300 mm wafers.
Moreover, the above method utilizes two expensive material technologies (i) epitaxial growth of a low-defect SiGe buffer layer and a strained Si layer, and (ii) layer transfer of the strain Si onto a handle substrate with an insulator.
Another method of forming strained-Si directly on an insulating layer involves growing a thick, relaxed SiGe layer having a thickness of about 400 nm or greater directly on a SOT wafer. The topmost region of the relaxed SiGe layer is typically designed to have the lowest threading defect density possible (either by step-grading the Ge content or other prior-art methods to reduce the dislocation density). The material below the topmost, relaxed, high-quality SiGe layer is then amorphized by ion-implantation at a dose and energy which reduces or annihilates the crystallinity in the region above the buried oxide layer and below the topmost, relaxed SiGe layer. Subsequent recrystallization annealing would be performed to solid-phase epitaxially regrow the amorphized region of the lattice from the topmost layer downwards. Because the topmost layer is relaxed, high-quality SiGe, recrystallization below this layer would propagate this lattice structure downwards. Therefore, the lowest layer, the original Si layer from the SOT substrate, recrystallizes with the in-plane lattice parameter of the topmost relaxed SiGe layer; and thus be strained in a tensile manner. The SiGe layer can then be selectively removed providing a strained, low-defect density SOT substrate for high-performance CMOS applications.
The main drawbacks to the abovementioned concept are 1) the questionable ability to grow high-quality thick relaxed SiGe alloy layers with low-enough defect density, 2) the questionable ability to recrystallize through a very thick random alloy without generating new defects, 3) the practical challenge of amorphizing such a large buried region with a conventional implant procedure and 4) minimizing the interdiffusion of Ge into the lower Si layer during all these processing steps.
T. Mizuno et al. “High Performance Strained-Si p-MOSFET on SiGe-on-Insulator Substrates Fabricated By SIMOX Technology”, International Electron Devices Meeting 1999, Technical Digest, p. 934, December 1999 provide another method of fabricating a sSOI substrate utilizing SIMOX and regrowth of a high-quality strained Si film. In particular, this prior art method begins by first growing a relaxed SiGe layer on a graded SiGe layer. Next, oxygen ions (180 keV, 4×1017 atoms/cm3) are implanted into the relaxed SiGe layer and thereafter a high temperature anneal (1350° C., 4 hours) is performed to grow a buried oxide within the SiGe layer. After implanting and annealing, a SiGe layer and a thick (20 nm) strained Si layer are regrown on the structure including the buried oxide. Despite being capable of forming an sSOI without wafer bonding or amorphization, this prior art technique requires separate regrowth steps to be performed after the SIMOX process that add additional processing steps and thus manufacturing costs in producing sSOI materials.
In view of the above, there is a need for providing new and improved methods of forming a strained semiconductor-on-insulator (SSOI) material that do not exhibit any of the drawbacks mentioned above. U.S. Ser. No. 10/883,887, filed Jul. 2, 2004 provides one such method of forming sSOI materials that avoids the drawbacks mentioned above. In the technique disclosed in the '887 application, the sSOI material is formed by first creating a buried porous layer underneath a strained semiconductor layer. The porous layer is then converted into a buried oxide layer by employing a high temperature oxidation/anneal step such that only a part of the strained semiconductor layer is consumed during processing.